Abstract

CMOS Macros for heterogeneous SoCs

Prof. Noll

Systems-on-chip (SoC) in future will feature a huge computational power by operating billions of transistors at GHz-clock frequencies. But aside of the well known advantages of systems-on-chip their exploding gate count complexity as well as the physical complexity of future deep-sub-micron technologies are facing SoC designers with serious issues. In order to overcome the inevitable problems due to exploding NRE costs the concept of SoC platforms is applied, allowing to share NRE costs among a high volume of fabricated devices.

This platform approach as well as other aspects like the ever decreasing time-to-market window, need for functionality updates etc. require a high degree of flexibility to be provided on future SoCs. The extensive use of SW-programmable kernels on SoCs offers the highest available flexibility but, although their performance continuously increases, suffers from a computational performance being too small for many applications and even more severe is paid for by an unacceptable power penalty. High performance blocks, dedicated to standard functionalities feature an orders of magnitude better power and area efficiency but no flexibility at all. Today there is a continuum of design styles being applied to design such dedicated blocks ranging from good old full custom to fully automated semi custom. As an exemplary vehicle, the optimization and design of a low-power high-performance transversal filter will be discussed in more detail. An additional implementation alternative attaining more and more attention is the use of re-configurable embedded FPGA (eFPGA) blocks which allow an attractive compromise between flexibility and efficiency. A really competitive SoC design indispensably requires a carefully selected mixture of these implementation alternatives in order to fulfil all requirements at a minimum of costs not limited to but particularly regarding silicon area and power dissipation. The underlying partitioning and mapping process in a very early design phase has to be performed on the basis of quantitative cost estimations and demands for sophisticated cost models and estimation strategies featuring an acceptable accuracy at reasonable efforts.

Zurück